Commit 20bab57e authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Commit Bot

media/gpu/v4l2: use upstream control V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR

Replace our own custom V4L2_CID_MPEG_VIDEO_H264_SPS_PPS_BEFORE_IDR with
V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR that serves the same purpose,
but is available upstream.

Since this control is not necessarily defined for older kernels, keep
our own definition in case it is missing to avoid breaking builds. The
control will just be reported as unavailable in this case.

BUG=b:167992324
TEST=Chromium builds for arm-generic

Change-Id: I5f210f76ea0cccf4f7efe606dc8b873c3d254bea
Reviewed-on: https://chromium-review.googlesource.com/c/chromium/src/+/2409058Reviewed-by: default avatarDavid Staessens <dstaessens@chromium.org>
Reviewed-by: default avatarChih-Yu Huang <akahuang@chromium.org>
Commit-Queue: Alexandre Courbot <acourbot@chromium.org>
Cr-Commit-Position: refs/heads/master@{#808769}
parent 01c65187
...@@ -1655,15 +1655,15 @@ bool V4L2VideoEncodeAccelerator::InitControls(const Config& config) { ...@@ -1655,15 +1655,15 @@ bool V4L2VideoEncodeAccelerator::InitControls(const Config& config) {
} }
if (output_format_fourcc_ == V4L2_PIX_FMT_H264) { if (output_format_fourcc_ == V4L2_PIX_FMT_H264) {
#ifndef V4L2_CID_MPEG_VIDEO_H264_SPS_PPS_BEFORE_IDR #ifndef V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR
#define V4L2_CID_MPEG_VIDEO_H264_SPS_PPS_BEFORE_IDR (V4L2_CID_MPEG_BASE + 388) #define V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR (V4L2_CID_MPEG_BASE + 644)
#endif #endif
// Request to inject SPS and PPS before each IDR, if the device supports // Request to inject SPS and PPS before each IDR, if the device supports
// that feature. Otherwise we'll have to cache and inject ourselves. // that feature. Otherwise we'll have to cache and inject ourselves.
if (device_->IsCtrlExposed(V4L2_CID_MPEG_VIDEO_H264_SPS_PPS_BEFORE_IDR)) { if (device_->IsCtrlExposed(V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR)) {
if (!device_->SetExtCtrls( if (!device_->SetExtCtrls(
V4L2_CTRL_CLASS_MPEG, V4L2_CTRL_CLASS_MPEG,
{V4L2ExtCtrl(V4L2_CID_MPEG_VIDEO_H264_SPS_PPS_BEFORE_IDR, 1)})) { {V4L2ExtCtrl(V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR, 1)})) {
NOTIFY_ERROR(kPlatformFailureError); NOTIFY_ERROR(kPlatformFailureError);
return false; return false;
} }
......
...@@ -281,7 +281,7 @@ class MEDIA_GPU_EXPORT V4L2VideoEncodeAccelerator ...@@ -281,7 +281,7 @@ class MEDIA_GPU_EXPORT V4L2VideoEncodeAccelerator
State encoder_state_; State encoder_state_;
// For H264, for resilience, we prepend each IDR with SPS and PPS. Some // For H264, for resilience, we prepend each IDR with SPS and PPS. Some
// devices support this via the V4L2_CID_MPEG_VIDEO_H264_SPS_PPS_BEFORE_IDR // devices support this via the V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR
// control. For devices that don't, we cache the latest SPS and PPS and inject // control. For devices that don't, we cache the latest SPS and PPS and inject
// them into the stream before every IDR. // them into the stream before every IDR.
bool inject_sps_and_pps_ = false; bool inject_sps_and_pps_ = false;
......
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