Require SSE3 on x86 platforms.

Before this CL, Chrome was built assuming SSE2 support on Windows,
Linux, Chrome OS, and Android. This CL raises the assumption to SSE3 on
all these platforms. This CL is a no-op for MSVC builds, which don't
have a way to explicitly target SSE3.

This CL does not impact Mac, where we only support 64-bit builds, which
allows us to assume SSSE3 support. (The first 64-bit Intel Mac used the
Core 2 microarchitecture.)

This CL will not have a usage impact on Chrome OS, which already assumes
SSE3 support, and on Android, where we require Lollipop+, which is only
used in phones with SSSE3+ support.

This CL will have a tiny impact on Windows and Linux usage. The impact
has been quantified and deemed acceptable. Impacted users are receiving
a notification starting in M87.

Confusingly, "SSSE3" is not a typo of "SSE3". It is the next step up
after SSE3, and before SSE4. This CL will cause Chrome to require SSE3.
Targeting SSSE3 is future work.

More details can be found in the design doc linked in the attached bug.

Bug: 1123353
Change-Id: If93aa9d37e75f3068b06c42f7412c7c4578f3b9f
Reviewed-on: https://chromium-review.googlesource.com/c/chromium/src/+/2311044Reviewed-by: Nico Weber <thakis@chromium.org>
Reviewed-by: Greg Thompson <grt@chromium.org>
Reviewed-by: Scott Violet <sky@chromium.org>
Commit-Queue: Victor Costan <pwnall@chromium.org>
Cr-Commit-Position: refs/heads/master@{#827575}

base/cpu_unittest.cc

@@ -20,6 +20,7 @@ TEST(CPU, RunExtendedInstructions) {
   ASSERT_TRUE(cpu.has_mmx());
   ASSERT_TRUE(cpu.has_sse());
   ASSERT_TRUE(cpu.has_sse2());
+  ASSERT_TRUE(cpu.has_sse3());
 
 // GCC and clang instruction test.
 #if defined(COMPILER_GCC)
@@ -32,10 +33,8 @@ TEST(CPU, RunExtendedInstructions) {
   // Execute an SSE 2 instruction.
   __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0");
 
-  if (cpu.has_sse3()) {
-    // Execute an SSE 3 instruction.
-    __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
-  }
+  // Execute an SSE 3 instruction.
+  __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
 
   if (cpu.has_ssse3()) {
     // Execute a Supplimental SSE 3 instruction.
@@ -80,10 +79,8 @@ TEST(CPU, RunExtendedInstructions) {
   // Execute an SSE 2 instruction.
   __asm psrldq xmm0, 0;
 
-  if (cpu.has_sse3()) {
-    // Execute an SSE 3 instruction.
-    __asm addsubpd xmm0, xmm0;
-  }
+  // Execute an SSE 3 instruction.
+  __asm addsubpd xmm0, xmm0;
 
   if (cpu.has_ssse3()) {
     // Execute a Supplimental SSE 3 instruction.

build/config/compiler/BUILD.gn

@@ -750,6 +750,7 @@ config("compiler_cpu_abi") {
       cflags += [
         "-m64",
         "-march=$x64_arch",
+        "-msse3",
       ]
       ldflags += [ "-m64" ]
     } else if (current_cpu == "x86") {
@@ -757,9 +758,8 @@ config("compiler_cpu_abi") {
       ldflags += [ "-m32" ]
       if (!is_nacl) {
         cflags += [
-          "-msse2",
           "-mfpmath=sse",
-          "-mmmx",
+          "-msse3",
         ]
       }
     } else if (current_cpu == "arm") {

build/config/win/BUILD.gn

@@ -118,6 +118,13 @@ config("compiler") {
       assert(false, "unknown current_cpu " + current_cpu)
     }
 
+    # Chrome currently requires SSE3. Clang supports targeting any Intel
+    # microarchitecture. MSVC only supports a subset of architectures, and the
+    # next step after SSE2 will be AVX.
+    if (current_cpu == "x86" || current_cpu == "x64") {
+      cflags += [ "-msse3" ]
+    }
+
     if (exec_script("//build/win/use_ansi_codes.py", [], "trim string") ==
         "True") {
       cflags += [

chrome/installer/setup/setup_util.cc

@@ -429,7 +429,7 @@ bool ContainsUnsupportedSwitch(const base::CommandLine& cmd_line) {
 
 bool IsProcessorSupported() {
 #if defined(ARCH_CPU_X86_FAMILY)
-  return base::CPU().has_sse2();
+  return base::CPU().has_sse3();
 #elif defined(ARCH_CPU_ARM64)
   return true;
 #else

third_party/abseil-cpp/symbols_x64_dbg.def

@@ -1336,7 +1336,6 @@ EXPORTS
     ??RStringReleaser@?M@???$?0V?$basic_string@DU?$char_traits@D@__1@std@@V?$allocator@D@23@@__1@std@@$0A@@Cord@absl@@QEAA@$$QEAV?$basic_string@DU?$char_traits@D@__1@std@@V?$allocator@D@23@@__1@std@@@Z@QEAAXVstring_view@2@@Z
     ??Sabsl@@YA?AVuint128@0@V10@@Z
     ??Tabsl@@YA?AVuint128@0@V10@0@Z
-    ??Uabsl@@YA?AVuint128@0@V10@0@Z
     ??XDuration@absl@@QEAAAEAV01@N@Z
     ??XDuration@absl@@QEAAAEAV01@_J@Z
     ??Xint128@absl@@QEAAAEAV01@V01@@Z

third_party/abseil-cpp/symbols_x86_dbg.def

@@ -1333,7 +1333,6 @@ EXPORTS
     ??RByUnixTime@Transition@cctz@time_internal@absl@@QBE_NABU1234@0@Z
     ??RStringReleaser@?M@???$?0V?$basic_string@DU?$char_traits@D@__1@std@@V?$allocator@D@23@@__1@std@@$0A@@Cord@absl@@QAE@$$QAV?$basic_string@DU?$char_traits@D@__1@std@@V?$allocator@D@23@@__1@std@@@Z@QAEXVstring_view@2@@Z
     ??Sabsl@@YA?AVuint128@0@V10@@Z
-    ??Uabsl@@YA?AVuint128@0@V10@0@Z
     ??XDuration@absl@@QAEAAV01@N@Z
     ??XDuration@absl@@QAEAAV01@_J@Z
     ??Xint128@absl@@QAEAAV01@V01@@Z