Recognize and enable collection for Tigerlake devices.

BUG=b:168615813

Change-Id: Ie4f7f2c13fd050ceeb28d8b70040ef0c34126e69
Reviewed-on: https://chromium-review.googlesource.com/c/chromium/src/+/2412831Reviewed-by: Ilya Sherman <isherman@chromium.org>
Reviewed-by: Gabriel Marin <gmx@chromium.org>
Commit-Queue: Gabriel Marin <gmx@chromium.org>
Cr-Commit-Position: refs/heads/master@{#807956}

chrome/browser/metrics/perf/cpu_identity.cc

@@ -57,6 +57,7 @@ const CpuUarchTableEntry kCpuUarchTable[] = {
     {"06_5E", "Skylake"},
     {"06_5F", "Goldmont"},    // Denverton
     {"06_7A", "GoldmontPlus"},
+    {"06_8C", "Tigerlake"},
     {"06_8E", "Kabylake"},
     {"06_9E", "Kabylake"},
     {"0F_03", "Prescott"},

chrome/browser/metrics/perf/cpu_identity_unittest.cc

@@ -49,6 +49,16 @@ TEST(CpuIdentityTest, DefaultCommandsBasedOnUarch_GoldmontPlus) {
   EXPECT_EQ("GoldmontPlus", GetCpuUarch(cpuid));
 }
 
+TEST(CpuIdentityTest, DefaultCommandsBasedOnUarch_Tigerlake) {
+  CPUIdentity cpuid;
+  cpuid.arch = "x86_64";
+  cpuid.vendor = "GenuineIntel";
+  cpuid.family = 0x06;
+  cpuid.model = 0x8c;  // Tiger Lake
+  cpuid.model_name = "";
+  EXPECT_EQ("Tigerlake", GetCpuUarch(cpuid));
+}
+
 TEST(CpuIdentityTest, DefaultCommandsBasedOnUarch_Excavator) {
   CPUIdentity cpuid;
   cpuid.arch = "x86_64";

chrome/browser/metrics/perf/perf_events_collector.cc

@@ -90,7 +90,7 @@ void ExtractVersionNumbers(const std::string& version,
 // Returns if a micro-architecture supports LBR callgraph profiling.
 bool MicroarchitectureHasLBRCallgraph(const std::string& uarch) {
   return uarch == "Haswell" || uarch == "Broadwell" || uarch == "Skylake" ||
-         uarch == "Kabylake";
+         uarch == "Kabylake" || uarch == "Tigerlake";
 }
 
 // Returns if a kernel release supports LBR callgraph profiling.
@@ -125,7 +125,7 @@ const char kPerfITLBMissCyclesCmdIvyBridge[] =
 const char kPerfDTLBMissCyclesCmdIvyBridge[] =
     "perf record -a -e dtlb_load_misses.walk_duration -g -c 160001";
 
-// TLB miss cycles for Skylake and Kabylake.
+// TLB miss cycles for Skylake, Kabylake, Tigerlake.
 const char kPerfITLBMissCyclesCmdSkylake[] =
     "perf record -a -e itlb_misses.walk_pending -c 30001";
 
@@ -157,7 +157,8 @@ const std::vector<RandomSelector::WeightAndValue> GetDefaultCommands_x86_64(
   const char* dtlb_miss_cycles_cmd = kPerfDTLBMissCyclesCmdIvyBridge;
   const char* lbr_cmd = kPerfLBRCmd;
 
-  if (cpu_uarch == "Skylake" || cpu_uarch == "Kabylake") {
+  if (cpu_uarch == "Skylake" || cpu_uarch == "Kabylake" ||
+      cpu_uarch == "Tigerlake") {
     itlb_miss_cycles_cmd = kPerfITLBMissCyclesCmdSkylake;
     dtlb_miss_cycles_cmd = kPerfDTLBMissCyclesCmdSkylake;
   }
@@ -171,8 +172,9 @@ const std::vector<RandomSelector::WeightAndValue> GetDefaultCommands_x86_64(
   if (cpu_uarch == "IvyBridge" || cpu_uarch == "Haswell" ||
       cpu_uarch == "Broadwell" || cpu_uarch == "SandyBridge" ||
       cpu_uarch == "Skylake" || cpu_uarch == "Kabylake" ||
-      cpu_uarch == "Silvermont" || cpu_uarch == "Airmont" ||
-      cpu_uarch == "Goldmont" || cpu_uarch == "GoldmontPlus") {
+      cpu_uarch == "Tigerlake" || cpu_uarch == "Silvermont" ||
+      cpu_uarch == "Airmont" || cpu_uarch == "Goldmont" ||
+      cpu_uarch == "GoldmontPlus") {
     cmds.push_back(WeightAndValue(50.0, kPerfCyclesCmd));
     // Haswell and newer big Intel cores support LBR callstack profiling. This
     // requires kernel support, which was added in kernel 4.4, and it was

chrome/browser/metrics/perf/perf_events_collector_unittest.cc

@@ -449,7 +449,40 @@ TEST_F(PerfCollectorTest, DefaultCommandsBasedOnUarch_Skylake) {
   cpuid.release = "3.18.0";
   std::vector<RandomSelector::WeightAndValue> cmds =
       internal::GetDefaultCommandsForCpu(cpuid);
-  ASSERT_GE(cmds.size(), 2UL);
+  ASSERT_GE(cmds.size(), 3UL);
+  EXPECT_EQ(cmds[0].value, kPerfCyclesCmd);
+  // We have both FP and LBR based callstacks.
+  EXPECT_EQ(cmds[1].value, kPerfFPCallgraphCmd);
+  EXPECT_EQ(cmds[2].value, kPerfLBRCallgraphCmd);
+  auto found =
+      std::find_if(cmds.begin(), cmds.end(),
+                   [](const RandomSelector::WeightAndValue& cmd) -> bool {
+                     return cmd.value == kPerfLBRCmd;
+                   });
+  EXPECT_NE(cmds.end(), found);
+  found = std::find_if(cmds.begin(), cmds.end(),
+                       [](const RandomSelector::WeightAndValue& cmd) -> bool {
+                         return cmd.value == kPerfLLCMissesPreciseCmd;
+                       });
+  EXPECT_NE(cmds.end(), found);
+  found = std::find_if(cmds.begin(), cmds.end(),
+                       [](const RandomSelector::WeightAndValue& cmd) -> bool {
+                         return cmd.value == kPerfITLBMissCyclesCmdSkylake;
+                       });
+  EXPECT_NE(cmds.end(), found);
+}
+
+TEST_F(PerfCollectorTest, DefaultCommandsBasedOnUarch_Tigerlake) {
+  CPUIdentity cpuid;
+  cpuid.arch = "x86_64";
+  cpuid.vendor = "GenuineIntel";
+  cpuid.family = 0x06;
+  cpuid.model = 0x8C;  // Tigerlake
+  cpuid.model_name = "";
+  cpuid.release = "5.4.64";
+  std::vector<RandomSelector::WeightAndValue> cmds =
+      internal::GetDefaultCommandsForCpu(cpuid);
+  ASSERT_GE(cmds.size(), 3UL);
   EXPECT_EQ(cmds[0].value, kPerfCyclesCmd);
   // We have both FP and LBR based callstacks.
   EXPECT_EQ(cmds[1].value, kPerfFPCallgraphCmd);